First-In-First-Out (FIFO) buffers are often used in serial interfaces such as Universal Asynchronous Receiver/Transmitters (UARTs) to buffer data. The FIFO buffer allows for longer latency when a processor needs to acquire data asynchronously without dropping data. Most digital output sensors have a simple serial port, such as Inter-IC (I2C) or Serial Peripheral Interface (SPI), which are read only occasionally without the need for a FIFO buffer to store samples.
A FIFO buffer is often implemented using an array of registers or flip-flops. Typically, FIFO buffers include a dual port memory in which one port is used to add new data and another port is used to read the older data. Each port adds additional gates and/or transistors, consequently consuming a relatively large area on a given chip. Area constraints placed on contemporary digital output sensors, such as small MEMS accelerometer digital output sensors, discourage the use of dual port memory. Sensor FIFO design is further complicated by the potential asynchronous timing between when reads and writes occur.